SSD1030P p-channel enhancement mode mosfet product summary v ds (v ) i d (a ) -30v -15a r ds(on) (m ? ) max 65 @v gs = - 10v 130 @v gs = - 4.5 v south sea semiconductor reserves the right to make changes to improve reliability or manufacturability without advance notice. south sea semiconductor , january 2008 (rev 2.1) 1 absolute maximum ra tings (t a = 25 c unless otherwise noted) therma l characteristics parameter symbol limi t uni t o drain-source vo ltage gate-source v oltage drain current-continuous @ t j = 125 c -pulsed drain-source diode forward current maximum power dissipation operating junction and storage t emperature range o a a a b v ds v gs i d i dm i s p d t j , t stg r ja -3 0 v v a a a c/ w w c o o 25 - + -1 5 -3 0 -1.7 50 -55 to 150 50 to -252 d g s fea tures super high density cell design for low r ds(on) . rugged and reliable. to -252 package. thermal resistance, junction-to-ambient d g s thermal resistance, junction-to-case r jc 3 115 @v gs = - 5 v pb free.
SSD1030P south sea semiconductor reserves the right to make changes to improve reliability or manufacturability without advance notice. south sea semiconductor , january 2008 (rev 2.1 ) 2 p-channel electrical characteristics (t a = 25 c unless otherwise noted) o unit symbol parameter condition mi n ty p ma x c zero gate v oltage drain current drain-source breakdown v oltage gate-body leakage gate threshold v oltage drain-source on-state resistance bv ds s i ds s i gs s v gs(th) r ds(on) v gs =0v , i d =-250 a v ds = -24v , v gs =0v v gs = 25v , v ds =0v v ds =v gs i d = -250 a v gs = -10v , i d = -15a v gs = -5 v , i d = -7.5a m v v a na -30 -1 100 -2.5 65 115 -1 55 100 on-state drain current forward t ransconductance t urn-on delay t ime rise t ime t urn-of f delay t ime fall t ime i d(on) g fs t d(on) t r t d(off) t f v ds = -5v , v gs = -10v v ds = -15v , i d = -5.5a v dd = -15 v, v ge n = -10 v, r l =15 6 7 35 23 8 ns p f s a input capacitance output capacitance reverse t ransfer capacitance c is s c os s c rs s v ds = -15v v gs =0v f=1.0mhz 450 110 60 t otal gate charge q g v ds =-15v , i d =-5.5a, v gs =-10v 9 i d = -1a, r ge n = 6 , diode forward v oltage v sd v gs =0v , i d = -1.0a v -0.8 -1.2 gate-source charge gate-drain charge q gs q gd i d = -5.5a, 1.5 2.5 v gs = -10v nc -1.9 v ds = -15 v, v ds =-15v , i d =-5.5a, v gs =-4.5v 5 notes a. surface mounted on fr4 board, t <10 sec. b. pulse t est pulse width < 300 s, duty cycle < 2% . c. guaranteed by design, not subject to production testing. - - - v gs = -4.5v , i d = -7.5a 110 130 -30
SSD1030P -v ds , drain-to-source v oltage (v) i - d ) a ( t n e r r u c n i a r d , figure 1. output characteristics 0 1 2 3 4 5 6 25 20 15 10 5 0 -v gs = 0v~2.5v -v gs , gate-to-source v oltage (v ) i - d ) a ( t n e r r u c n i a r d , figure 2. thansfer characteristics 0 0.8 1.6 2.4 3.2 4.0 4.8 25 20 15 10 5 0 - 5 5 c o 25 c o tj = 125 c o r , ) n o ( s d e c n a t s i s e r - n o ( d e z i l a m r o n ) -55 -25 0 25 50 75 100 125 1. 8 1. 6 1. 4 1.2 1.0 0.8 0. 6 figure 4. on-resistance va riation with t emperatur e v gs = -10v t j , junction t empertature ( c ) o i d = -5.5 a -v ds , drain-to-source v oltage (v) ) f p ( e c n a t i c a p a c , c figure 3. capacitanc e 0 5 10 15 20 25 3 0 c i s s c o s s c r s s 750 0 600 450 300 150 d e z i l a m r o n , h t v e g a t l o v d l o h s e r h t e c r u o s - e t a g tj , junction t emperature ( c ) figure 5. gate threshold va riatio n with t emperature o -50 -25 0 25 50 75 100 125 v ds = v gs i d = -250 a 1. 3 1. 2 1. 1 1. 0 0. 9 0. 8 0. 7 0.6 v b s s d d e z i l a m r o n , g a t l o v n w o d k a e r b e c r u o s - n i a r d e figure 6. breakdown vo ltage va riatio n with t emperatur e tj , junction t emperature ( c ) o -50 -25 0 25 50 75 100 12 5 1.15 1.10 1.05 1.0 0 0.9 5 0.9 0 0.85 i d = -250 a -v gs = 3.5v -v gs = 10.5v~4.5v south sea semiconductor reserves the right to make changes to improve reliability or manufacturability without advance notice. south sea semiconductor , january 2008 (rev 2.1) 3
SSD1030P -i ds , drain-source current (a ) g , s f ) s ( e c n a t c u d n o c s n a r t 0 5 10 15 2 0 figure 7. t ransconductance va riation with drain current i - s ) a ( t n e r r u c n i a r d - e c r u o s , 20. 0 -v sd , body diode forward vo ltage (v ) figure 8. body diode forward vo ltage va riation with source current 0.3 0.5 0.7 0.9 1.1 1. 3 v - s g ) v ( e g a t l o v e c r u o s o t e t a g , figure 9. gate charge qg , t otal gate charge (nc) 0 1.5 3 4.5 6 7.5 9 10.5 1 2 10 8 6 4 2 0 v ds = -15v i d = -5.5a i d ) a ( t n e r r u c n i a r d , -v sd , drain-to-source v oltage (v ) figure 10. maximum saf e operating area 10 8 6 4 2 0 10. 0 0. 0 t j = 25 c o 1. 0 v ds = -15v south sea semiconductor reserves the right to make changes to improve reliability or manufacturability without advance notice. south sea semiconductor , january 2008 (rev 2.1) 4 0.01 0.10 1.00 10.00 100.00 100 10 0. 1 0.01 1 r ds(on) l imit v gs = 10v single pulse r ja = 9 6 o c/ w t a = 2 5 o c 100 s 1m s 10m s dc 1 100m s 10 s
SSD1030P figure 11 . switching t est circuit v gs r gen v out v dd v in d r l g s figure 12. switching wa veforms inver ted pulse width t r t d(on) v out v in t on t of f t d(of f) t f 10% 50% 50% 90% 10% 90% 10% 90% figure 13. normalized thermal t ransient impedance curve r e v i t c e f f e d e z i l a m r o n , ) t ( e c n a d e p m i l a m r e h t t n e i s n a r t square wa ve pulse duration (sec) south sea semiconductor reserves the right to make changes to improve reliability or manufacturability without advance notice. south sea semiconductor , january 2008 (rev 2.1) 5 0.00 1 0.01 0. 1 1 0.001 0.01 0. 1 1 10 100 1000 r ja (t) = r(t) * r ja r ja = 96 c/w t j - t a = p * r ja (t ) duty cycle, d = t 1 / t 2 p(pk ) t 1 t 2 single pulse 0.01 0.02 0.05 0. 1 0. 2 d = 0. 5
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